The DisplayPort standards published by the Video Electronics Standards Association (VESA) describe digital display interfaces used to connect video sources, e.g., graphics processing units (GPUs), to display devices, e.g., computer monitors. DisplayPort interfaces include 1 to 4 lanes over which high-speed, packetized data are transmitted (e.g., 1.62, 2.7, or 5.4 Gigabits per second per lane).
One advantage of DisplayPort over previous display interface standards is that it includes link training that enables the transmitter in the source to adapt to different cable lengths. That is, because of the signal degradation that occurs as the transmitted data propagate over the cable, a training sequence determines an appropriate level of “preemphasis” to apply to the higher frequency components of the data signal at the output buffer(s) of the transmitter to ensure that a sufficient signal level reaches the receiver at the other end of the cable.
Conventional high-speed transmitters in DisplayPort-compliant display interfaces employ either pure current-mode buffers or pure voltage-mode buffers as output buffers to apply the necessary levels of preemphasis. Conventional current-mode buffers are effective in high-speed transmitters but can consume an undesirably high amount of current for some applications. Conventional voltage-mode buffers are also effective and consume significantly less current than their current-mode counterparts. However, there is a design tradeoff with voltage-mode buffers between tunability and complexity. That is, in order to achieve a level of tunability comparable to current-mode buffers (i.e., to achieve the desired levels of preemphasis for different conditions) the complexity of the output buffer design may become unacceptably high.